Web Analytics
Part Datasheet Search > Logic Gates > CD4077 Datasheet PDF
Images are for reference

CD4077 Datasheet PDF

Part Series:
CD4077 Series
Category:
Logic Gates
Description:
XNOR Gate 4Element 2IN CMOS 14Pin SOIC T/R
Updated Time: 2023/01/13 01:58:46 (UTC + 8)

CD4077 Datasheet PDF Logic Gates

31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOP T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin CDIP Tube
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin PDIP Tube
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin TSSOP T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin TSSOP T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOIC Tube
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOP T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOIC T/R
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin SOIC Tube
31 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin TSSOP T/R
30 Pages
TI
IC QUAD EXCLUSV-NOR GATE 14TSSOP
30 Pages
TI
IC QUAD EXCLUSV-NOR GATE 14TSSOP
29 Pages
TI
XNOR Gate 4Element 2IN CMOS 14Pin CDIP Tube

CD4077BM96 Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
14 Pin
Supply Voltage (DC)
3.00V ~ 18.0V
Case/Package
SOIC-14
Number of Outputs
1 Output
show more

CD4077BM96 Function Overview

Description
The Harris CD4070B contains four independent Exclusive OR gates. The Harris CD4077B contains four independent Exclusive-NOR gates.
The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively.
Features
• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
   - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
   - 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range)
   - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices
Applications
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
show more
Part Datasheet PDF Search
Loading...
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.

Relate Parts