HMC987LP5E Datasheet PDF - ADI

●The HMC987LP5E is a 1-to-9 low noise Fan-out Buffer designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall time of <100ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SerDes devices. The noise floor is particularly important in these applications, when the clock network bandwidth is wide enough to allow square wave switching. The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs and 1 CML output with adjustable swing/power-level in 3dB steps.

● One adjustable power CML/RF output

● Serial or parallel control, hardware chip-enable

● LVPECL, LVDS, CML and CMOS Compatible inputs

● Up to 8 differential or 16 single-ended LVPECL outputs

● <1µA Power down current

● -166dBc/Hz at 2GHz Ultra-low noise floor