SN74AUP1G74DCUR Datasheet PDF - TI

●The SN74AUP1G74DCUR is a single positive-edge-triggered D-type Flip-flop designed for 0.8 to 3.6V VCC operation. A low level at the preset (PRE\\) or clear (CLR\\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. When both the CLR\ and PRE\ inputs are set low, the CLR\ input will override the PRE\ input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

● Low noise - Overshoot and undershoot <10% of VCC

● Ioff Supports partial-power-down mode operation

● Schmitt-trigger action allows slow input transition and better switching noise immunity

● Suitable for point-to-point applications

● Latch-up performance exceeds 100mA per JESD 78, Class II

● 3.6V I/O Tolerant to support mixed-mode signal operation

● 5ns at 3.3V Maximum tpd

● 0.9µA Maximum low static-power consumption

● 5.5pF Typical low dynamic-power consumption

● 1.5pF Typical low input capacitance

● Green product and no Sb/Br