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LAN8700 Datasheet PDF

Part Series:
LAN8700 Series
Category:
Interface ICs
Description:
PHY 1CH 10Mbps/100Mbps 3.3V 36Pin QFN EP Tray
Updated Time: 2023/01/13 02:27:05 (UTC + 8)

LAN8700 Datasheet PDF Interface ICs

74 Pages
SMC
Ethernet ICs HIPERFRM ETHRNT PHY
74 Pages
Microchip
PHY 1CH 10Mbps/100Mbps AUTOMOTIVE 36Pin QFN EP
14 Pages
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 36Pin QFN EP

LAN8700IC-AEZG Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
36 Pin
Supply Voltage (DC)
3.00V (min)
Operating Voltage
3V ~ 3.6V
Case/Package
QFN-36
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LAN8700IC-AEZG Function Overview

The LAN8700IC-AEZG is a low-power variable I/O voltage Analogue Interface IC with HP auto-MDIX support for high-performance embedded Ethernet applications. The LAN8700i can be configured to operate on a single 3.3V supply utilizing an integrated 3.3 to 1.8V linear regulator. An option is available to disable the linear regulator to optimize system designs that have a 1.8V power plane. The LAN8700i consists of an encoder/decoder, scrambler/descrambler, wave-shaping transmitter, output driver, twisted-pair receiver with adaptive equalizer and baseline wander (BLW) correction and clock and data recovery functions. The LAN8700i can be configured to support either the media independent interface (MII) or the reduced media independent interface (RMII). The LAN8700i is compliant with IEEE 802.3-2005 standards (MII Pins tolerant to 3.6V) and supports both IEEE 802.3-2005 compliant and vendor-specific register functions.
Single-chip Ethernet physical layer transceiver (PHY)
ESD protection levels of ±8kV HBM without external protection devices
ESD protection levels of EN/IEC61000-4-2
Comprehensive flexPWR® technology
Flexible power management architecture
+1.6 to +3.6V LVCMOS variable I/O voltage range
Integrated 3.3V to 1.8V regulator for optional single supply operation
Regulator can be disabled if 1.8V system supply
Performs HP Auto-MDIX in accordance with IEEE 802.3ab specification
Cable length greater than 150m
Automatic polarity correction
Latch-up performance exceeds 150mA per EIA/JESD 78, class II
Energy detect power-down mode
Low current consumption power-down mode
Low operating current consumption
39mA Typical in 10BASE-T and 79mA typical in 100BASE-TX mode
Supports auto-negotiation and parallel detection
Supports the media independent interface (MII) and reduced media independent interface (RMII)
Compliant with IEEE 802.3-2005 standards - MII pins tolerant to 3.6V
IEEE 802.3-2005 compliant register functions
ESD sensitive device, take proper precaution while handling the device.
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