●Description
●The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications.
●Features
●• Integer Unit Based on SPARC V7 High-performance RISC Architecture
●• Optimized Integrated 32/64-bit Floating-point Unit
●• On-chip Peripherals
● – EDAC and Parity Generator and Checker
● – Memory Interface
● Chip Select Generator
● Waitstate Generation
● Memory Protection
● –DMA Arbiter
● –Timers
● General Purpose Timer (GPT)
● Real-time Clock Timer (RTCT)
● Watchdog Timer (WDT)
● – Interrupt Controller with 5 External Inputs
● – General Purpose Interface (GPI)
● – Dual UART
●• Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface
●• IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
●• Fully Static Design
●• Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz
●• Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs
●• Operating Range: 4.5V to 5.5V (1) -55°C to +125°C
●• Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019
●• SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)
●• No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm2
●• Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540
●• Package: 256 MQFPF; Bare Die
