74HC173PW,118 Datasheet PDF - NXP

●The 74HC173PW is a quad positive-edge trigger D-type Flip-flop with 3-state outputs. This high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). This 4-bit parallel load register with clock enable control, 3-state buffered outputs (Q0 to Q3) and master reset (MR). When the two data enable inputs (E1\ and E2\\) are low, the data on the Dn inputs is loaded into the register synchronously with the low-to-high clock transition. When one or both En\ inputs are high one set-up time prior to the low-to-high clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the low-to-high clock transition. The master reset input (MR) is an active high asynchronous input. When MR is high, all four flip-flops are reset (cleared) independently of any other input condition.

● Gated input enable for hold (do nothing) mode

● Gated output enable control

● Edge-triggered D-type register

● Asynchronous master reset

● Bus driver output capability

● Complies with JEDEC standard No. 7A