74LV138D,112 Datasheet PDF - NXP

●The 74LV138D is a 3-to-8 inverting Decoder/Demultiplexer pin and function compatible with 74HC138 and 74HCT138. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive active low outputs (Y0\ to Y7\\). There are three enable inputs: two active low (E1\ and E2\\) and one active high (E3). Every output will be high unless E1\ and E2\ are low and E3 is high. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The 74LV138 can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active high or low state.

● Optimized for low voltage applications

● Demultiplexing capability

● Multiple input enable for easy expansion

● Ideal for memory chip select decoding

● Active low mutually exclusive outputs