C161OLMHABXUMA1 Datasheet PDF - Infineon

● High Performance 16-bit CPU with 4-Stage Pipeline

● 80 ns Instruction Cycle Time at 25 MHz CPU Clock

● 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

● Enhanced Boolean Bit Manipulation Facilities

● Additional Instructions to Support

● 16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns

● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

● Clock Generation via prescaler or via direct clock input

● On-Chip Memory Modules

● 2 KBytes On-Chip Internal RAM (IRAM) on C161O 1 KByte IRAM on C161K

● On-Chip Peripheral Modules

● Two Multi-Functional General Purpose Timer Units with 5 Timers on C161O, one Timer Unit with 3 Timers on C161K

● Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

● Up to 4 MBytes External Address Space for Code and Data

● Programmable External Bus Characteristics for Different Address Ranges

● Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width

● Idle and Power Down Modes

● Programmable Watchdog Timer

● Up to 63 General Purpose I/O Lines

● On-Chip Bootstrap Loader

● 80-Pin MQFP Package