CD74AC280M96G4 Datasheet PDF - TI

●Description

●The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (∑E output is HIGH) when an even number of data inputs is HIGH. Odd parity is indicated (∑O output is HIGH) when an odd number of data inputs is HIGH. Parity checking for words larger than nine bits can be accomplished by tying the ∑E output to any input of an additional ’AC280, ’ACT280 parity checker.

●Features

●• Buffered Inputs

●• Typical Propagation Delay

●   - 10ns at VCC = 5V, TA = 25oC, CL = 50pF

●• Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015

●• SCR-Latchup-Resistant CMOS Process and Circuit Design

●• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption

●• Balanced Propagation Delays

●• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply

●• ±24mA Output Drive Current

●   - Fanout to 15 FAST™ ICs

●   - Drives 50Ω Transmission Lines