●The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz.
●The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals.
●The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit interval). For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.
●Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the VDDREF terminal.
●The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.
●The CDC5801A device is characterized for operation over free-air temperatures of 40°C to 85°C.
● Low Jitter Clock Multiplier by x4, x6, x8. Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz
● Fail-Safe Power Up Initialization
● Low Jitter Clock Divider by /2, /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency From 12.5 MHz to 62.5 MHz
● 2.6 mUI Programmable Bidirectional Delay Steps
● Typical 8-ps Phase Jitter (12 kHz to 20 MHz) at 500 MHz
● Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) at 500 MHz
● One Single-Ended Input and One Differential Output Pair
● Output Can Drive LVPECL, LVDS, and LVTTL
● Three Power Operating Modes to Minimize Power
● Low Power Consumption (Typical 200 mW at 500 MHz)
● Packaged in a Shrink Small-Outline Package (DBQ)
● No External Components Required for PLL
● Spread Spectrum Clock Tracking Ability to Reduce EMI
● Applications: Video Graphics, Gaming Products, Datacom, Telecom
● Accepts LVCMOS, LVTTL Inputs for REFCLK Terminal
● Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper VDDREF Voltage Level (For Example, HSTL 1.5 if VDDREF = 1.6 V)
● Supports Industrial Temperature Range of -40°C to 85°C
