●General Description
●The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional Sinput ANDed with the primary Sinput. A LOW on any Sinput while the Rinput is HIGH will be stored in the latch and appear on the corresponding Q output as a HIGH. A LOW on the Rinput while the Sinput is HIGH will clear the Q output to a LOW. Simultaneous transition of the Rand Sinputs from LOW-toHIGH will cause the Q output to be indeterminate. Both inputs are voltage level triggered and are not affected by
●transition time of the input data.
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IC TRANSCEIVER 3-ST 8Bit 20SOIC
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Bus XCVR Single 8CH 3-ST 20Pin PDIP W Rail
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AND Gate 4Element 2IN Bipolar 14Pin SOIC N T/R
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Latch Transparent 3-ST 8CH D-Type 20Pin SOIC W T/R
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NAND Gate 3Element 3IN Bipolar 14Pin SOIC
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74ALS TTL, SMD, 74ALS373, SOIC20; Logic Type: Transparent Latch; No. of Outputs: 8; Supply Voltage Range: 4.5V to 5.5...
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IC TRANSCEIVER 3-ST 8Bit 20SOIC
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Bus XCVR Single 8CH 3-ST 20Pin SSOP Rail
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NAND Gate 1Element 8IN Bipolar 14Pin PDIP W Rail
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Buffer/Line Driver 8CH Inverting 3-ST Bipolar 20Pin SOIC W T/R
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