DS21552LN+ Datasheet PDF - Maxim Integrated

● Complete DS1/ISDN-PRI/J1 transceiver functionality

● Long and Short haul LIU

● Crystal-less jitter attenuator

● Generates DSX-1 and CSU line build-outs

● HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation

● Dual two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz

● 8.192MHz clock output locked to RCLK

● Interleaving PCM Bus Operation

● Per-channel loopback and idle code insertion

● 8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola)

● Programmable output clocks for Fractional T1

● Fully independent transmit and receive functionality

● Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes

● IEEE 1149.1 JTAG-Boundary Scan

● Pin compatible with DS2152/54/354/554 SCTs

● 100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply; low power CMOS