●The GC4116 quad transmit chip contains four identical up-conversion channels. The up-convert channels accept real or complex signals, interpolate them by programmable amounts ranging from 32 to 5,792, and modulates them up to selected center frequencies. The modulated signals are then summed together and optionally summed with modulated signals from other GC4116 chips. Channels can be used in pairs to reduce the interpolation ratio down to 16 in order to process wider band input signals.
●Each channel contains a user programmable input filter (PFIR) which can be used to shape the transmitted signals spectrum, or can be used as a Nyquist transmit filter for shaping digital data such as QPSK, GMSK or QAM symbols.
●The up-converter channels are designed to maintain over 115 dB of spur free dynamic range. Each up-convert channel accepts 16 bit inputs (bit serial) and produces 20 bit outputs. The up-converter outputs are summed with an external 22 bit input to produce a single 22 bit output. The chip can output either real or complex data. The frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can the gain of each circuit. Each channel interpolates by the same amount, but can be programmed with independent PFIR coefficients. Channels can be synchronized to support beamformed or frequency hopped systems.
●An independent resampler block performs resampling on up to 4 signals. The resampler has its own input and output pins so that it can be used independently from the up-convert channels. The resampler engine is identical to the one in the gc4016. It provides a user programmable filter up to 512 taps long and allows for sampling by arbitrary amounts with delay resolutions up to 64 time phases.
●A serial controller block is used to generate serial clocks and frame strobes for the channel and resampler input ports. This block simplifies interfacing the GC4116 to other devices.
●On chip diagnostic circuits are provided to simplify system debug and maintenance.
●The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chips 110 control registers (8 bits each) and five coefficient RAMs are memory mapped into the 5 bit address space of the control port using an internal page register.
● Output rates up to 106 MSPS
● Four identical up-convert channels
● 16 bit real or complex inputs
● Four bit serial input ports, or memory mapped input registers
● Serial interface controller simplifies interfacing with ASICs or DSP chips
● Resampler circuit filters, pulse shapes and resamples data to allow arbitrary input to output sample rate conversion
● Interpolation factors of
● 32 to 5,792 in each channel
● 16 to 32 by combining two channels
● Independent frequency, phase and gain controls
● User programmable 63 tap input filter
● 0.02 Hz tuning resolution
● 115 dB Spur Free Dynamic Range
● 90 dB or more image rejection
● 0.07 dB gain resolution
● 0.05 dB peak to peak passband ripple
● The four channels are summed into a single output signal
● 22 bit sum I/O path to merge outputs from multiple GC4116 chips
● 8 to 22 bit 2s complement or offset binary output samples
● Accepts QPSK or QAM symbol data directly, performs transmit (pulse shape) filtering
● Performs pulse shaping and phase equalization for IS95 and CDMA2000
● Exceeds Damps, GSM, & IS95 requirements
● Supports up to two 4 Mbaud channels.
● Microprocessor interface for control
● Built in diagnostics
● Each GC4116 chip upconverts:
● Four GSM, DAMPS, or IS95 carriers, or
● Two 3X CDMA2000 carriers, or
● Two 3.84MB UMTS carriers
● Power consumption at 70 MHz, 2.5 volts:
● 84 mW per DAMPS channel
● 107 mW per GSM channel
● 305mW per 3.84MB UMTS channel
● Industrial temperature range (40C to +85C)
● GC4116PB 160 ball PBGA (15mm by 15mm) package
● 3.3volt I/O voltage, 2.5volt core voltage
● JTAG Boundary Scan
