K9F5608U0C-PIB0 Datasheet PDF - Samsung

●GENERAL DESCRIPTION

●Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0C is 256M bit with spare 8M bit capacity. The device is offered in 1.8V or 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200ms on a 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word.  The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even thewrite intensive systems can take advantage of the K9F56XXX0C¢s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.