LM3S6965-IQC50B0 Datasheet PDF - ETC2

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●Luminary Micro, Inc.

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●Architectural Overview

●The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

●Product Features

●The LM3S6965 microcontroller includes the following product features:

●■ 32-Bit RISC Performance

●– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications

●– System timer (SysT ick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

●– Thumb®-compatible Thumb-2-only instruction set processor core for high code density

●– 50-MHz operation

●– Hardware-division and single-cycle-multiplication

●– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

●– 38 interrupts with eight priority levels

●– Memory protection unit (MPU), providing a privileged mode for protected operating system functionality

●– Unaligned data access, enabling data to be efficiently packed into memory

●– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control

●■ Internal Memory

●– 256 KB single-cycle flash

●• User-managed flash block protection on a 2-KB block basis

●• User-managed flash data programming

●• User-defined and managed flash-protection block

●– 64 KB single-cycle SRAM

●■ General-Purpose Timers

●– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.

●  Each GPTM can be configured to operate independently:

●• As a single 32-bit timer

●• As one 32-bit Real-Time Clock (RTC) to event capture

●• For Pulse Width Modulation (PWM)

●• T o trigger analog-to-digital conversions

●– 32-bit Timer modes

●• Programmable one-shot timer

●• Programmable periodic timer

●• Real-Time Clock when using an external 32.768-KHz clock as the input

●• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug

●• ADC event trigger

●– 16-bit Timer modes

●• General-purpose timer function with an 8-bit prescaler

●• Programmable one-shot timer

●• Programmable periodic timer

●• User-enabled stalling when the controller asserts CPU Halt flag during debug

●• ADC event trigger

●– 16-bit Input Capture modes

●• Input edge count capture

●• Input edge time capture

●– 16-bit PWM mode

●• Simple PWM mode with software-programmable output inversion of the PWM signal

●■ ARM FiRM-compliant Watchdog Timer

●– 32-bit down counter with a programmable load register

●– Separate watchdog clock with an enable

●– Programmable interrupt generation logic with interrupt masking

●– Lock register protection from runaway software

●– Reset generation logic with an enable/disable

●– User-enabled stalling when the controller asserts the CPU Halt flag during debug

●■ 10/100 Ethernet Controller

●– Conforms to the IEEE 802.3-2002 Specification

●– Full- and half-duplex for both 100 Mbps and 10 Mbps operation

●– Integrated 10/100 Mbps Transceiver (PHY)

●– Automatic MDI/MDI-X cross-over correction

●– Programmable MAC address

●– Power-saving and power-down modes

●■ Synchronous Serial Interface (SSI)

●– Master or slave operation

●– Programmable clock bit rate and prescale

●– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

●– Programmable interface operation for Freescale SPI, MICROWIRE, or T exas Instruments synchronous serial interfaces

●– Programmable data frame size from 4 to 16 bits

●– Internal loopback test mode for diagnostic/debug testing

●■ UART

●– Three fully programmable 16C550-type UART s with IrDA support

●– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading

●– Programmable baud-rate generator with fractional divider

●– Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface

●– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

●– Standard asynchronous communication bits for start, stop, and parity

●– False-start-bit detection

●– Line-break generation and detection

●■ ADC

●– Single- and differential-input configurations

●– Four 10-bit channels (inputs) when used as single-ended inputs

●– Sample rate of one million samples/second

●– Flexible, configurable analog-to-digital conversion

●– Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs

●– Each sequence triggered by software or internal event (timers, analog comparators, PWM or GPIO)

●– On-chip temperature sensor

●■ Analog Comparators

●– Two independent integrated analog comparators

●– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence

●– Compare external pin input to external pin input or to internal programmable voltage reference

●T arget Applications

●■ Remote monitoring

●■ Electronic point-of-sale (POS) machines

●■ T est and measurement equipment

●■ Network appliances and switches

●■ Factory automation

●■ HVAC and building control

●■ Gaming equipment

●■ Motion control

●■ Medical instrumentation

●■ Fire and security