●GENERAL DESCRIPTION
●The MACH® 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
●Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.
●FEATURES
●◆ High logic densities and I/Os for increased logic integration
● — 128 to 512 macrocell densities
● — 68 to 256 I/Os
●◆ Wide selection of density and I/O combinations to support most application needs
● — 6 macrocell density options
● — 7 I/O options
● — Up to 4 I/O options per macrocell density
● — Up to 5 density & I/O options for each package
●◆ Performance features to fit system needs
● — 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
● — 182 MHz fCNT
● — Four programmable power/speed settings per block
●◆ Flexible architecture facilitates logic design
● — Multiple levels of switch matrices allow for performance-based routing
● — 100% routability and pin-out retention
● — Synchronous and asynchronous clocking, including dual-edge clocking
● — Asynchronous product- or sum-term set or reset
● — 16 to 64 output enables
● — Functions of up to 32 product terms
●◆ Advanced capabilities for easy system integration
● — 3.3-V & 5-V JEDEC-compliant operations
● — IEEE 1149.1 compliant for boundary scan testing
● — 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
● — PCI compliant (-5/-6/-7/-10/-12 speed grades)
● — Safe for mixed supply voltage system design
● — Bus-Friendly™ Inputs & I/Os
● — Individual output slew rate control
● — Hot socketing
● — Programmable security bit
●◆ Advanced E2CMOS process provides high performance, cost effective solutions
●◆ Supported by ispDesignEXPERT™ software for rapid logic development
● — Supports HDL design methodologies with results optimized for MACH 5 devices
● — Flexibility to adapt to user requirements
● — Software partnerships that ensure customer success
●◆ Lattice and Third-party hardware programming support
● — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment
● — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
Part 3D Model
