NB3L8543SDTR2G Datasheet PDF - ON Semiconductor

●The NB3L8543S is a high performance, low skew 1−to−4 LVDS Clock Fanout Buffer. The NB3L8543S features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The CLK_SEL pin will select the differential CLK and CLKb inputs when LOW (or left open and pulled LOW by the internal pull−down resistor). When CLK_SEL is HIGH, the differential PCLK and PCLKb inputs are selected. The common clock enable pin, CLK_EN, is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse on the outputs during asynchronous assertion/deassertion of the clock enable pin. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.

●Features

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● Four Differential LVDS Output Pairs

● Two Selectable Differential Clock Inputs

● CLK/CLKb Can Accept LVPECL, LVDS, HCSL, HSTL and SSTL

● PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL

● Maximum Output Frequency: 650 MHz

● Additive Phase Jitter, RMS: 50 fs (typical)

● Output Skew: 40 ps (maximum)

● Part−to−part Skew: 200 ps (maximum)

● Propagation Delay: 1.9 ns (maximum)