NB3N1900K Datasheet PDF - ON Semiconductor

●The NB3N1900K differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point−to−point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI & UPI), PCIe Gen1, Gen2, Gen3, Gen4. The NB3N1900K internal PLL is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1900K supports HCSL output levels.

●Features

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● Fixed Feedback Path for Lowest Input−to−Output Delay

● Eight Dedicated OE# Pins for Hardware Control of Outputs

● PLL Bypass Configurable for PLL or Fanout Operation

● Selectable PLL Bandwidth

● Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI

● SMBus Programmable Configurations

● 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 /Gen 4 and Intel QPI & UPI Phase Jitter

● 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)

● Cycle−to−Cycle Jitter: < 50 ps

● Output−to−Output Skew: < 65 ps

● Input−to−Output Delay: Fixed at 0 ps

● Input−to−Output Delay Variation: < 50 ps

● Phase Jitter: PCIe Gen3 < 1 ps rms

● Phase Jitter: PCIe Gen4 < 0.5 ps rms

● Phase Jitter: QPI 9.6GB/s < 0.2 ps rms

● QFN 72−pin Package, 10 mm x 10 mm

● These are Pb−Free Devices