P87C52X2FBD,157 Datasheet PDF - NXP

●The P87C52X2FBD,157 is a 8-bit Microcontroller based on high-performance static 80C51 designs incorporating high-density CMOS technology. The device support both 6-clock and 12-clock operation. The device contain 256 byte RAM, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART and on-chip oscillator and clock circuits. In addition, the devices are low power static designs which offer a wide range of operating frequencies down to zero. Two software selectable modes of power reduction idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.

● 80C51 Central processing unit

● 12 Clock operation with selectable 6-clock operation

● Memory addressing capability - Up to 64kB ROM and 64kB RAM

● Clock can be stopped and resumed

● Idle mode

● Power-down mode

● CMOS and TTL compatible

● 2 Speed ranges at VCC = 5V - 0 to 30MHz with 6-clock operation, 0 to 33MHz with 12-clock operation

● Dual data pointers

● Security bits - ROM (2 bits), OTP (3 bits)

● Encryption array - 64 bytes

● Four interrupt priority levels

● Six interrupt sources

● Four 8-bit I/O ports

● Full-duplex enhanced UART

● Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)

● Programmable clock-out pin

● Asynchronous port reset

● Low EMI (inhibit ALE, slew rate controlled outputs and 6-clock mode)

● Wake-up from Power Down by an external interrupt