PCA9516APW,112 Datasheet PDF - NXP

●The PCA9516APW,112 is a CMOS Integrated Circuit intended for application in I²C-bus and SMBus systems. While retaining all the operating modes and features of the I²C-bus system, it permits extension of the I²C-bus by buffering both the data (SDAn) and the clock (SCLn) lines, thus enabling five buses of 400pF. The I²C-bus capacitance limit of 400pF restricts the number of devices and bus length. Using the PCA9516A enables the system designer to divide the bus into five segments off of a hub where any segment-to-segment transition sees only one repeater delay. It can also be used to run different buses at 5 and 3.3V or 400 and 100kHz buses where the 100kHz bus is isolated when 400kHz operation of the other bus is required. Two or more PCA9516As cannot be put in series. The PCA9516A design does not allow this configuration.

● 5-channel Bidirectional buffer

● I²C-bus and SMBus compatible

● Active high individual repeater enable input

● Open-drain input/outputs

● Lock-up free operation

● Supports arbitration and clock stretching across the repeater

● Accommodates standard-mode and fast-mode I²C-bus devices and multiple masters

● Powered-OFF high-impedance I²C-bus pins

● Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA