●Architecture Overview
●The pASIC 3 family of devices have a range of 4,000 to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic’s“ patented ViaLink“ technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.
●Device Highlights
●High Performance & High Density
●• Up to 60,000 usable PLD gates with up to 316 I/Os
●• 300 MHz 16-bit counters, 400 MHz datapaths
●• 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes
●Easy to Use/Fast Development Cycles
●• 100% routable with 100% utilization and complete pin-out stability
●• Variable-grain logic cells provide high performance and 100% utilization
●• Comprehensive design tools include high quality Verilog/VHDL synthesis
●Advanced I/O Capabilities
●• Interfaces with 3.3 V and 5.0 V devices
●• PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades
●• Full JTAG boundary scan
●• I/O cells with individually controlled registered input path and output enables
●Up to 316 I/O Pins
●• Up to 308 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for 1/-2/-3/-4 speed grades
●• Up to eight high-drive input/distributed network pins
●Up to Eight Low-Skew Distributed
●Networks
●• Two array clock/control networks are available to
●the logic cell flip-flop; clock, set, and reset inputs
●— each can be driven by an input-only pin
●• Up to six global clock/control networks are available to the logic cell; F1, clock, set, and reset
●inputs and the data input, I/O register clock, reset, and enable inputs as well as the output enable control — each can be driven by an input only pin, I/O pin, any logic cell output, or I/O cell feedback
●High Performance
●• Input + logic cell + output total delays under 6 ns
●• Data path speeds over 400 MHz
●• Counter speeds over 300 MHz
