SI53340-B-GM Datasheet PDF - Silicon Labs

●The SI53340-B-GM is a 4-output ultra-low jitter LVDS Buffer features a 2:1 input mux making it ideal for redundant clocking applications. Utilizing Silicon Laboratories advanced fan-out clock technology, the Si53340 guarantees low additive jitter, low skew and low propagation delay variability from DC to 1250MHz. It features minimal cross-talk and excellent supply noise rejection, simplifying low jitter clock distribution in noisy environments. It has universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL and CML. For the best high-speed performance, the use of differential formats is recommended. For both single ended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance.

● 4 LVDS outputs

● 45fs RMS Ultra-low additive jitter

● 2:1 Input mux

● Universal input stage accepts differential or LVCMOS clock