SN74AC373PWR Datasheet PDF - TI

●The SN74AC373PWR is an octal Transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The eight latches are D-type transparent latches. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pull-up components.

● Full parallel access for loading

● Maximum tpd of 9.5ns at 5V

● 3-state Noninverting outputs drive bus lines directly

● Green product and no Sb/Br