SN74ALS138ADG4 Datasheet PDF - TI

●description

●The ′ALS138A and ′AS138 are 3-line to 8-line decoders/demultiplexers designed for high performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible.

●\- Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems

●\- Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

●\- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs