●This 18-bit (dual-octal) noninverting registered transceiver is designed for 2.7-V to 3.6-V VCC operation.
●The SN74ALVC16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.
●The SN74ALVC16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or
●CLKENBA\\) inputs. It also provides parity-enable (SEL\\) and parity-select (ODD/EVEN\\) inputs and separate error-signal (ERRA\ or ERRB\\) outputs for checking parity. The direction of data flow is controlled by OEAB\ and OEBA\\. When SEL\ is low, the parity functions are enabled. When SEL\ is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
●Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
●The SN74ALVC16901 is available in TI"s thin shrink small-outline (DGG) package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
●The SN74ALVC16901 is characterized for operation from -40°C to 85°C.
● Member of the Texas Instruments
●_Widebus+_
●TM Family
●_EPIC_
●TM (Enhanced-Performance Implanted CMOS) Submicron Process
●_UBT_
●TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
● Simultaneously Generates and Checks Parity
● Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
● Distributed V
●CC
● and GND Pin Configuration Minimizes High-Speed Switching Noise
● Latch-Up Performance Exceeds 250 mA
●Per JEDEC Standard JESD-17
● Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
● Packaged in Thin Shrink Small-Outline (DGG) Package
●Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
