SN74AS373N Datasheet PDF - TI

●The SN74AS373N is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

● Full parallel access for loading

● Buffered control inputs

● PNP Inputs reduce DC loading on data lines