SN74LV573APWT Datasheet PDF - TI

●description/ordering information

●The ’LV573A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation.

●These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

●• 2-V to 5.5-V VCC Operation

●• Max tpd of 8 ns at 5 V

●• Typical VOLP (Output Ground Bounce)

●   <0.8 V at VCC = 3.3 V , TA = 25°C

●• Typical VOHV (Output VOH Undershoot)

●   >2.3 V at VCC = 3.3 V , TA = 25°C

●• Support Mixed-Mode Voltage Operation on All Ports

●• Ioff Supports Partial-Power-Down Mode Operation

●• Latch-Up Performance Exceeds 250 mA Per JESD 17

●• ESD Protection Exceeds JESD 22

●   − 2000-V Human-Body Model (A114-A)

●   − 200-V Machine Model (A115-A)

●   − 1000-V Charged-Device Model (C101)