SN74LVTH573PWR Datasheet PDF - TI

●description/ordering information

●These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

●The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

●• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)

●• Support Unregulated Battery Operation Down to 2.7 V

●• Typical VOLP (Output Ground Bounce)

●   <0.8 V at VCC = 3.3 V, TA = 25°C

●• Ioff and Power-Up 3-State Support Hot Insertion

●• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

●• Latch-Up Performance Exceeds 500 mA Per JESD 17

●• ESD Protection Exceeds JESD 22

●   − 2000-V Human-Body Model (A114-A)

●   − 200-V Machine Model (A115-A)