TMS320F28376DZWTT Datasheet PDF - TI

● Dual-Core Architecture

● Two TMS320C286 32-Bit CPUs

● 200 MHz

● IEEE 754 Single-Precision Floating-Point

● Trigonometric Math Unit (TMU)

● Viterbi/Complex Math Unit (VCU-II)

● Two Programmable Control Law Accelerators (CLAs)

● 200 MHz

● IEEE 754 Single-Precision Floating-Point Executes Code Independently of Main CPU

● On-Chip Memory

● 512KB or 1MB of Flash (ECC-Protected)

● 172KB or 204KB of RAM (ECC or Parity)

● Dual-Zone Security Supporting Third-Party Development

● Clock and System Control

● Two Internal Zero-Pin 10-MHz Oscillators

● On-Chip Crystal Oscillator and External Clock Input

● Windowed Watchdog Timer Module

● Missing Clock Detection Circuitry

● 1.2-V Core, 3.3-V I/O Design

● System Peripherals

● Two External Memory Interfaces (EMIFs) With ASRAM and SDRAM Support

● Dual 6-Channel Direct Memory Access (DMA) Controller

● Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering

● Hardware (HW) Interrupt Controller

● Multiple Low-Power Mode Support With External Wakeup

● JTAG Emulation Connection

● Communications Peripherals

● USB 2.0 (MAC + PHY)

● Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface

● Two Controller Area Network, D_CAN, Modules (Pin-Bootable)

● Three High-Speed (40-MHz) SPI Ports (Pin-Bootable)

● Two Multichannel Buffered Serial Ports (McBSPs)

● Four Serial Communications Interfaces (SCIs) (Pin-Bootable)

● Two I2C Interfaces (Pin-Bootable)

● Analog Subsystem

● Four Dual-Mode Analog-to-Digital Converters (ADCs)

● 16-Bit Mode

● 1.1 MSPS Each (up to 4.4-MSPS System)