TMS470R1VF4B8 Datasheet PDF - TI

●The TMS470R1VF4B8 device is a member of the Texas Instruments TMS470R1x family of general-purpose16/ 32-bit reduced instruction set computer (RISC) microcontrollers. The VF4B8 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF4B8 utilizes the bigendian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.

●High-end embedded control applications demand more performance from their controllers while maintaining low costs. The VF4B8 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

●The VF4B8 device contains the following:

● ARM7TDMI 16/32-Bit RISC CPU TMS470R1x system module (SYS) with 470+ enhancements 256K-byte flash 16K-byte SRAM Zero-pin phase-locked loop (ZPLL) clock module Digital watchdog (DWD) timer Real-time interrupt (RTI) module Multi-buffered serial peripheral interface (MibSPI) module Serial peripheral interface (SPI) module Two serial communications interface (SCI) modules Two standard CAN controllers (SCC) 10-bit multi-buffered analog-to-digital converter (MibADC), with 16 input channels High-end timer (HET) controlling 9 I/Os External Clock Prescale (ECP) Up to 47 I/O pins

●The functions performed by the 470+ system module (SYS) include: address decoding; memory protection; memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal interrupt sources; device clock control; and parallel signature analysis (PSA). The enhanced real-time interrupt (RTI) module on the VF4B8 has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the _TMS470R1x System Module Reference Guide_ (literature number SPNU189).

●The VF4B8 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

●The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 64 MHhz. For more detailed information on the flash, see the flash section of this data sheet and the _TMS470R1x F05 Flash Reference Guide_ (literature number SPNU213).

●The VF4B8 device has six communication interfaces: a MibSPI, an SPI, two SCIs, and two SCCs. The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length to be shifted into and out of the device at a programmed bit-transfer rate. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices.The SCI is a fullduplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. For more information on the MibSPI peripheral, see the _TMS470R1x Multi-Buffered Serial Peripheral Interface (MibSPI) Reference Guide_ (literature number SPNU217). For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197).

●The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the _TMS470R1x High-End Timer (HET) Reference Guide_ (literature number SPNU199). The VF4B8 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be sired together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the _TMS470R1x High-End Timer (HET) Reference Guide_ (literature number SPNU199).

●The VF4B8 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the _TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide_ (literature number SPNU206).

●The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF4B8 device modules. For more detailed functional information on the ZPLL, see the _TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide_ (literature number SPNU212).

●The VF4B8 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the _TMS470R1x External Clock Prescaler (ECP) Reference Guide_ (literature number SPNU202).

● High-Performance Static CMOS Technology

● TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)

● 24-MHz System Clock (64-MHz Pipeline Mode)

● Independent 16/32-Bit Instruction Set

● Open Architecture With Third-Party Support

● Built-In Debug Module

● Integrated Memory

● 256K-Byte Program Flash

● One Bank With 10 Contiguous Sectors

● 16K-Byte Static RAM (SRAM)

● Operating Features

● Core Supply Voltage (VCC): 1.81 V - 2.06 V

● Core Supply Voltage (VCC): 1.70 V - 2.06 V

●When Used At or Below 56MHz, 85C Ambient Temp, and 115C Junction Temp

● I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V

● Low-Power Modes: STANDBY and HALT

● Industrial/Automotive Temperature Ranges

● 470+ System Module

● 32-Bit Address Space Decoding

● Bus Supervision for Memory/Peripherals

● Digital Watchdog (DWD) Timer

● Enhanced Real-Time Interrupt (RTI)

● System Integrity and Failure Detection

● Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler

● Multiply-by-4 or -8 Internal ZPLL Option

● ZPLL Bypass Mode

● Six Communication Interfaces:

● Serial Peripheral Interface (SPI)

● 255 Programmable Baud Rates

● Two Serial Communication Interfaces (SCIs)

● 224 Selectable Baud Rates

● Asynchronous/Isosynchronous Modes

● Two Standard CAN Controllers (SCC)

● 16-Mailbox Capacity

● Fully Compliant With CAN Protocol, Version 2.0B

● Multi-Buffered Serial Peripheral Interface (MibSPI)

● 64-Word Buffer

● Eight Chip Selects

● High-End Timer (HET)

● 9 Programmable I/O Channels:

● 7 High-Resolution Pins

● High-Resolution Share Feature (XOR)

● High-End Timer RAM

● 128-Instruction Capacity

● External Clock Prescale (ECP) Module

● Programmable Low-Frequency External Clock (CLK)

● 16-Channel 10-Bit Multi-Buffered ADC (MibADC)

● 64-Word FIFO Buffer

● Single- or Continuous-Conversion Modes

● 1.55 µs Minimum Sample and Conversion Time

● Calibration Mode and Self-Test Features

● 10 Dedicated General-Purpose I/O (GIO) Pins and 37 Additional Peripheral I/Os

● Eight External Interrupts

● Flexible Interrupt Handling

● Compatible ROM Device (Planned)

● On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (JTAG) Test-Access Port

● 100-Pin Plastic Low-Profile Quad Flatpack

● Development System Support Tools Available

● Code Composer Studio™ Integrated Development Environment (IDE)

● HET Assembler and Simulator

● Real-Time In-Circuit Emulation

● Flash Programming

●Code Composer Studio is a trademark of Texas Instruments.

●ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).

●All trademarks are the property of their respective owners.

●The test-access port is compatible with the IEEE Standard 1149.1-1990, _IEEE Standard Test-Access Port and Boundary Scan Architecture_ specification. Boundary scan is not supported on this device.

●ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.