●The TSB43AB22APDT is a Link Layer Controller (LLC) integrated with 1394a, 400Mbps and 2-port physical layer (PHY). It is capable of transferring data between the 33MHz PCI bus and the 1394 bus at 400Mbps. The TSB43AB22A device provides two 1394 ports that have separate cable bias (TPBIAS). The TSB43AB22A device also supports the IEEE standard 1394a-2000 power-down features for battery-operated applications and arbitration enhancements. As required by the 1394 open host controller interface specification (OHCI) and IEEE standard 1394a-2000, internal control registers are memory-mapped and non-prefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and it provides plug-and-play (PnP) compatibility. Furthermore, the TSB43AB22A device is compliant with the PCI bus power management interface specification as specified by the PC 2001 design guide requirements. The TSB43AB22A device supports the D0, D1, D2 and D3 power states.
● Ultra-low-power sleep mode
● Cable ports monitor line conditions for active connection to remote node
● Cable power presence monitoring
● Separate cable bias (TPBIAS) for each port
● 1.8V Core logic with universal PCI interfaces compatible with 3.3V & 5V PCI signalling environments
● Physical write posting of up to three outstanding transactions
● PCI burst transfers and deep FIFOs to tolerate large host latency (PCI_CLKRUN) protocol
● External cycle timer control for customized synchronization
● Extended resume signalling for compatibility with legacy DV devices
● PHY-link logic performs system initialization and arbitration functions
● PHY-link encode and decode functions included for data-strobe bit level encoding
● PHY-link incoming data resynchronized to local clock
● Node power class information signalling for system power management
● Serial ROM interface supports 2-wire serial EEPROM devices
● Two general-purpose I/Os
● Fabricated in advanced low-power CMOS process
● PCI and CardBus register support
● Isochronous receive dual-buffer mode
● Out-of-order pipelining for asynchronous transmit requests
● Register access fail interrupt when the PHY SCLK is not active
Part 3D Model
