●The UCC2752x family of devices are dual-channel, high-speed, low-side gate driver devices capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 17 ns. In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. The input pin thresholds are based on CMOS logic, which is a function of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. The Enable pins are based on TTL and CMOS compatible logic, independent of VDD supply voltage.
●The UCC27528 is a dual noninverting driver. UCC27527 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family to ensure that outputs are held low when input pins are in floating condition. UCC27528 features Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active high logic and can be left open for standard operation.
● Industry-Standard Pin Out
● Two Independent Gate-Drive Channels
● 5-A Peak Source and Sink Drive Current
● CMOS Input Logic Threshold (Function of
●Supply Voltage on VDD Pins)
● Hysteretic Logic Thresholds for High Noise
●Immunity
● Independent Enable Function for Each Output
● Inputs and Enable Pin Voltage Levels Not
●Restricted by VDD Pin Bias Supply Voltage
● 4.5-V to 18-V Single Supply Range
● Outputs Held Low During VDD UVLO (Ensures
●Glitch-Free Operation at Power Up and Power
●Down)
● Fast Propagation Delays (17-ns Typical)
● Fast Rise and Fall Times (7-ns and 6-ns Typical)
● 1-ns Typical Delay Matching Between 2 Channels
● Outputs Held in Low When Inputs Floating
● SOIC-8, and 3-mm × 3-mm WSON-8 Package Options
● Operating Temperature Range of 40°C to 140°C
● 5-V Negative Voltage Handling Capability on Input Pins
