●Overview
●The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
●The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications
●Features
●· Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
●· Fast clock rate: 200/183/166/143/125/100 MHz
●· Self refresh mode: standard and low power
●· Internal pipelined architecture
●· 512K word x 16-bit x 2-bank
●· Programmable Mode registers
● - CAS# Latency: 1, 2, or 3
● - Burst Length: 1, 2, 4, 8, or full page
● - Burst Type: interleaved or linear burst
● - Burst stop function
●· Individual byte controlled by LDQM and UDQM
●· Auto Refresh and Self Refresh
●· 4096 refresh cycles/64ms
●· CKE power down mode
●· JEDEC standard +3.3V±0.3V power supply
●· Interface: LVTTL
●· 50-pin 400 mil plastic TSOP II package
●· 60-ball, 6.4x10.1mm VFBGA package
●· Lead Free Package available for both TSOP II and VFBGA
Part 3D Model
