●description
●This octal registered transceiver is designed for 2.7-V to 3.6-V VCCoperation. The SN74LVC543 contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEABor LEBA) and output-enable (OEABor OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEABis low and
●LEABis low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEABplaces the A latches in the storage mode. With CEABand OEABboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B but uses CEBA, LEBA, and OEBA.
●To ensure the high-impedance state during power up or power down, OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
●The SN74LVC543 is characterized for operation from –40°C to 85°C.
●EPIC(Enhanced-Performance Implanted CMOS) Submicron Process
●Typical VOLP(Output Ground Bounce)
● < 0.8 V at VCC= 3.3 V, TA= 25°C
●Typical VOHV(Output VOHUndershoot)
● > 2 V at VCC= 3.3 V, TA= 25°C
●Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
●Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
