$ 0

CDCLVD110 Programming Manual - TI

Manufacturer:

Description:

1-to-10 LVDS clock buffer up to 900MHz with minimum skew for clock distributionN

Pictures:

3D Model

Symbol

Footprint

Pinout

Product Pictures

Pages guide:

Block Diagram onP2

Package Outline Dimension onP9P11P12

Marking Information onP9

Packaging Infomation onP9P10P11P12

Specifications onP3

Application Area onP1P14

Electrical Specification onP3P4

Click page to view the detail

CDCLVD110 Documents

14 Pages / 0.5 MByte

72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.

Matching parts

Alternative parts

Warning risks

Computing costs

File format: *.xlsx, *.xls, *.csv